The present invention relates to a semiconductor device having a MOS transistor which is excellent in driving force and a method of fabricating the same.
The recent development of a highly integrated semiconductor device or so-called VLSI has required increasing miniaturization of MOS transistors as constituents of the VLSI. In the MOS transistors, an attempt has been made to reduce the dimensions of devices in different generations in accordance with scaling rules. In response to the reduced dimensions, substrate concentration has been increased to suppress a so-called short-channel effect and thereby improve the properties of the devices.
Among various dimensions of the device, however, the depth of an impurity layer as a source or drain is difficult to reduce. Under such circumstances, a structure for suppressing the short-channel effect has been proposed for a MOS transistor.
As a conventional embodiment, the structure of a MOS transistor shown in, e.g., "High-Performance Devices for a 0.15 .mu.m CMOS technology (G. G. Shahidi et al, IEEE Electron Device Letters, vol. 14, no. 10, October 1993)" (hereinafter simply referred to as the conventional MOS transistor) and a fabrication method therefor will be described with reference to FIG. 20.
As shown in FIG. 20, the conventional MOS transistor comprises: a p.sup.- -type well region 2 formed in a semiconductor substrate 1; a p-type channel region 3 formed in a surface portion of the semiconductor substrate 1; a gate electrode 5 formed on the channel region 3 with a gate insulating film 4 interposed therebetween, source/drain regions 9 composed of n.sup.+ -type impurity layers formed in the respective regions of the surface portion of the semiconductor substrate 1 which are located on both sides of the gate electrode 5, extension regions 6 composed of n.sup.+ -type impurity layers formed inwardly of the source/drain regions 9 in the surface portion of the semiconductor substrate 1, and p.sup.+ -type pocket regions 7 formed in the surface portion of the semiconductor substrate 1 to cover the extension regions 6 and have an upper end portion extending to the gate insulating film 4.
The conventional MOS transistor comprises the p.sup.+ -type pocket regions 7 formed to cover the n.sup.+ -type extension regions 6. Since the pocket regions 7 inhibit depletion layers from extending from the n.sup.+ -type extension regions 6 and the source/drain regions 9, the short-channel effect can be suppressed.
Even if the depth of the extension region 6 or of the source/drain regions 9 cannot be reduced in accordance with the scaling rules, the short-channel effect can be suppressed by increasing impurity concentration in the pocket regions 7.
However, the conventional MOS transistor has the following problems.
First Problem
If impurity concentration in the p.sup.+ -type pocket regions is increased to further suppress the short-channel effect, impurity concentration in the extension regions is reduced as a result of cancellation, since the n.sup.+ -type extension regions are covered with the pocket regions. This causes the problem that the resistance of the extension regions is increased and the driving force of the MOS transistor is thereby decreased. If impurity concentration in the p.sup.+ -type pocket regions is increased, impurity concentration in the portions of the channel region adjacent the extension regions is also increased so that impurity scattering in a carrier flow is aggravated and the mobility of carriers is lowered. This further decreases the driving force of the MOS transistor. If impurity concentration in the portions of the channel region adjacent the extension regions is increased, a so-called reverse short-channel effect occurs to cause the problem that the threshold voltage of the transistor is largely dependent on the channel length of the transistor.
Second Problem
Sidewalls are formed by depositing, after the extension regions are formed by implanting n-type impurity ions and the pocket regions are formed by implanting p-type impurity ions, an insulating film over the entire surface of the semiconductor substrate at a low temperature of 600.degree. C. to 850.degree. C. for a period of several tens of minutes to several hours, and then performing anisotropic etching with respect to the insulating film. However, transient enhanced diffusion of the impurity is caused remarkably by point defects (voids and interstitial silicons) produced during the implantation of the impurity ions. This increases impurity concentration in the pocket regions so that the resistance of the extension regions increases and the mobility of carriers lowers. This decreases the driving force of the MOS transistor. Moreover, the interstitial silicons produced during the ion implantation for forming the extension regions and the pocket regions are diffused toward the gate insulating film during the low-concentration heat treatment (e.g., during the deposition of the insulating film as the sidewalls), so that a gradient is produced in the distribution. As a consequence, the impurity in the end portion of the channel region adjacent the gate electrode moves toward the substrate surface, which increases impurity concentration in the surface region of the end portion of the channel region adjacent the gate electrode. This causes the so-called reverse short-channel effect and varies the threshold voltage disadvantageously. The phenomenon is conspicuous when the pocket regions are formed by implanting boron ions.
Third Problem
In the method of fabricating the conventional MOS transistor, the p.sup.+ -type pocket regions are amorphized by implanting indium ions therein such that the distribution of arsenic ions in the n.sup.+ -type extension regions is sharpened.
However, the present inventors have newly found that a heat treatment performed after the amorphizing step causes point defects in the inner portions of the pocket regions adjacent the pn junction formed between the extension regions and the pocket regions (i.e., outside the extension regions). The point defects produced in the pocket regions cause a junction leakage current. If a VLSI having such a MOS transistor is incorporated into mobile communication equipment, there occurs the problem that the junction leakage current increases power consumption during standby.